* Proj 24 32bit Floating Point Arithmetic Unit * Proj 23 Ripple Carry and Carry Skip Adders * Proj 22 AMBA AHB compliant Memory Controller * Proj 21 Synthesis of Asynchronous Circuits * Proj 20 ATM Knockout Switch Concentrator * Proj 18 Power Efficient Logic Circuit Design * Proj 17 High Speed Multiplier Accumulator Using SPST
* Proj 16 PROCESSOR ARCHITECTURES FOR MULTIMEDIA * Proj 15 VLSI Architecture For Removal Of Impulse Noise In Image * Proj 14 LOSSLESS DATA COMPRESSION HARDWARE ARCHITECTURE * Proj 13 HIGH SPEED MULTIPLIER USING SPURIOUS POWER SUPPRESSION * Proj 12 Universal Cryptography Processorfor Smart Cards * Proj 11 HIGH SPEED 4 BIT SFQ MULTIPLIER * Proj 10 Speeding Up Fault Injection Campaigns on Safety Critical Circuits * Proj 9 Fast Hardware Design Space Exploration * Proj 8 Face Detection System Using Haar Classifiers
#311 transistor b sides software#
* Proj 7 Hardware Software Runtime Environment for Reconfigurable Computers * Proj 4 Design Space Exploration Of Field Programmable Counter * Proj 3 Router Architecture for Junction Based Source Routing * Proj 1 Modulator for digital terrestrial television according to the DTMB standard * Modes of Asynchronous Sequential Machines * Design Procedure for Asynchronous Sequential Circuits * Design of Asynchronous Sequential Machine * Analysis of Asynchronous Sequential Machines * ASM Chart Tool for Sequential Circuit Design * three terminal fixed voltage regulator ics * three terminal adjustable voltage regulator ics * adjustable negative voltage regulator ics * non saturated type precision half wave rectifier This is the major disadvantage of pass transistors. Hence when the pass transistor pulls a node to high logic the output only changes upto VDD–VTh. As discussed NMOS devices are effective in passing strong '0' but it is poor at pulling a node to VDD. The another advantage of pass transistor logic is the lower capacitance because of reduced number of transistors.
If we compare this with the same AND gate implementation using pass transistor logic the number of transistors required are four including the two transistor required to invert the input B. To illustrate this consider the implementation of AND gate using complementary CMOS logic. The major advantage of pass transistor logic is that fewer transistors are required to implement a given function. This satisfies the truth table of AND gate reproduced in Table below for verification. When B is low the right NMOS pass transistor is turned ON and passes a '0' to the output F. In this gate if the B input is high the left NMOS is turned ON and copies the input A to the output F. In complementary CMOS logic primary inputs are allowed to drive only gate terminals.įigure below shows implementation of AND function using only NMOS pass transistors. The Pass transistor logic is required to reduce the transistors for implementing logic by using the primary inputs to drive gate terminals, source and drain terminals.